1. Field of the Invention
The invention relates generally to Content Addressable Memory (CAM) logic. More particularly, the invention relates to improving the density and performance of CAMs.
2. Description of the Related Art
Content Addressable Memory (CAM) logic examines a data word and compares this data with internally stored data. This is a very common operation in high performance processors, as the result of the comparison is utilized to control the machine flow (e.g., determine what the machine will do next).
FIG. 1 illustrates a typical structure of a Content Addressable Memory (CAM) register. Multiple words (m in this example) of data are stored in different entries 102 of the register. Each word has n bits of data 101. Thus, there are m.times.n memory elements (CAM) in this register. At the top of the register, there is a control block 100 that enables the comparison and stores the result. For any particular entry in the register, the comparison will indicate a mismatch if any of the bits of input data 104 is different from the data stored in it.
An example of a current Content Addressable Memory (CAM) implementation will now be described with reference to FIG. 2. FIG. 2 is a schematic diagram illustrating a prior Content Addressable Memory implementation. The top of the figure shows how the comparison is enabled, and the comparison result is evaluated. Node 210 is pre-charged HIGH, and conditionally discharged if there is a mismatch in any bit when the evaluation is enabled. The bottom of the figure shows how the enable is distributed to all n bits of the register entry, and, in each one of them, it is connected to evaluation bias circuit 206. This circuit consists of n-MOS transistors 204 and 205. Transistor 204 is connected to the enable 200, and transistor 205 is connected to the result of the comparison 209 (doing a logic AND of both of them). When the enable is ON (clock HIGH), if the comparison in any bit of the register indicates a mismatch between the data stored 207 and the data input 208, node 210 is discharged and 201 indicates the mismatch. The bit comparison is computed by 211, a transmission gate XOR gate.